The invention relates to a semiconductor device having at least one memory cell comprising a semiconductor body having a surface region of a first conductivity type which is covered with a thick insulating layer. An aperture is provided in the insulating layer at the area of a storage element of the memory cell, which storage element comprises a capacitor having a first plate of electrically conductive material and a part of the semiconductor body which is separated from the first plate by a dielectric and which forms a second plate of the capacitor and is connected to a semiconductor zone of a second conductivity type opposite to the first via a channel region controllable by a gate electrode. The insulating layer is thicker than the dielectric and the gate electrode is electrically connected to a first selection line of conductive material of the memory cell, said selection line extending to above the semiconductor zone which forms part of a second selection line of the memory cell.
Such semiconductor devices are used in dynamic memories, for example, in computers, microprocessors and various other devices for data storage and data handling.
A semiconductor device of the above-mentioned kind is disclosed in Japanese Patent Application No. 53-76687. The device described in that Application comprises a memory cell which is realized in an aperture in a layer of thick oxide present on the semiconductor body. The memory cell consists inter alia of a storage capacitor which is connected by means of a controllable channel region to a semiconductor zone of a conductivity type opposite to that of the semiconductor body. The conductivity state of the channel region is determined by the voltage at a gate electrode at the area of the conduction channel, which gate electrode is connected electrically to a first selection line of the memory cell. The semiconductor zone forms part of a second selection line of the memory cell.
The first selection line is provided so that within the aperture in the thick oxide it crosses the second selection line and is separated therefrom by a thin layer of oxide. This gives rise to a high stray capacitance and associated capacitive coupling between the two selection lines. This coupling may result in the memory cell in question being wrongly selected or incorrect information being written or read.
Moreover, the device shown in the Japanese Patent Application comprises so-called channel stopping regions, zones of the same conductivity type as the semiconductor body but having a higher doping of impurities so as to prevent channel formation between various memory cells. The semiconductor zone which forms part of the second selection line is generally very highly doped so as to prevent too high a series resistance in the selection line.
In the prior art device the semiconductor zone adjoins a channel stopping region and forms a p-n junction therewith. As a result of the mutual high impurity dopings, said p-n junction will have a comparatively low breakdown voltage. In addition, said p-n junction represents an extra stray capacitance, the value of which will be higher as the doping in the channel stopping region becomes higher.